When electronic devices are formed on a target object, e.g., a semiconductor wafer (hereinafter, referred to as “wafer”), a wafer is consecutively processed in a plurality of process modules of a processing system due to a complex and integrated structure of the electronic devices. In an exemplary processing system, a plurality of process modules is provided around transfer modules. In this case, a plurality of processes can be consecutively performed on the wafer by loading and unloading the wafer into and from the respective process modules. For example, Japanese Patent Application Publication No. 2007-149973 suggests a processing system in which the number of process modules of the processing system is increased by connecting a plurality of transfer modules.
In the multi-cluster type processing system, various types of plasma processes can be performed on the wafer by using a plurality of process modules. In the case of performing the plasma processes by using a plurality of process modules, a single wafer may be loaded into and unloaded from at least one of the process modules multiple times. A processing in which a single wafer is loaded into and unloaded from at least one of the process modules multiples times and processed in the same process module multiple times is referred to as a recursive processing.
Japanese Patent No. 4477982 discloses a technique of unloading a wafer from each of process modules in accordance with a maximum processing time during consecutive processes in the process modules on the assumption that an accurate processing time in each of the process modules can be estimated in advance and a recursive processing is not performed in each of the process modules.
However, if the recursive processing is performed in at least one of the process modules, there may be a rate-limiting process module and the transfer delay of the wafer may be occurred in processing and transferring the wafer before the rate-limiting process module. In order to prevent the transfer delay of the wafer, it is required to accurately estimate the processing time and the transfer time of the wafer. However, in the multi-cluster type processing system for performing various types of plasma processes, when the processes include the recursive processing, it is currently difficult and impractical to accurately estimate the processing time and the transfer time of the wafer.